We provide the infrastructure and process for developing and using efficient digital simulation environments. Our systems incorporate intelligent and reusable modular transaction-based components based on SystemVerilog methodologies such as UVM, OVM and VMM. We work with various simulation platforms such as those from Cadence, Synopsys, Mentor and Aldec to provide a system template and a process to quickly and easily produce complete and flexible verification systems to suit a dynamic range of needs for FPGA or ASIC flows of any size, from initial integration scripted tests to complete coverage-driven randomized regression suits. |